Redundant Arrays Of Inexpensive Disks (RAID) systems are well known systems which can help increase availability of stored data in network storage systems. Such systems typically include several hard disk drives which store data in such a way that, if one disk drive fails, data is still able to be recovered from the system. Such systems generally have a network storage bridge, which acts as an interface between a host computer and an array of disk drives. To further enhance the availability of data in such a system, it is common to have redundant storage controllers within the network storage bridge, such that if one controller fails, the remaining controller is able to continue read and write operations to the array of disk drives.
In a fully redundant storage bridge, user data has to be temporarily stored twice, once in a primary controller of data and once in its redundant or secondary counterpart. In this setup if the primary controller is damaged and unable to continue operation, the secondary redundant controller has a copy of the user data. Thus data is available if one controller fails, because either the primary or the secondary copy of the data will be delivered to its final destination, the array of disk drives.
Typically and with reference to the prior art drawing of FIG. 1, when a primary controller 10 receives user data to be stored in the disk array 14, it builds description tables in the process. These tables describe the data size, location and it's destination. The primary controller 10 then initiates a data transfer, known as a mirroring operation, in which the data is transferred to the secondary controller 18. Once the mirroring operation is complete, the primary controller 10 sends an indication to the host computer 22 that the data write is complete. Thus, the host computer 22 is notified that the data is stored, while the data may not be written to the disk array 14 for a period of time.
A traditional method for mirroring data between controllers is for the primary controller 10 to notify the secondary controller 18 that data is going to be mirrored. The primary controller 10 then transfers metadata to the secondary controller 18. The metadata is the data which is contained in the description tables. Following the metadata, the primary controller 10 transfers the user data to the secondary controller 18. The user data is stored in a local memory 26 associated with the primary controller 10 for transfer to a remote memory 30 associated with the secondary controller 18. In some cases, these transfers are initiated using direct memory access (DMA) and a DMA engine 34. In such a situation, a processing portion 38 within the primary controller 10 will give the DMA engine 34 a transfer command to transfer data from the primary controller 10 to the secondary controller 18. This transfer command typically includes the data contained in the description tables, which identifies the data which is to be transferred to the secondary controller 18. The processing portion 38 generally builds a DMA table containing the data from the description tables, which is able to be used by the DMA engine 34. This DMA table is then loaded into the DMA engine 34, with the transfer command. The DMA engine 34 receives the data from the processing portion 38, stores it in a memory 42 associated with the DMA engine 34, and then conducts the data transfer.
As can be seen, the processing portion 38 must build a DMA table, and transfer the table from the processing portion to the DMA engine 34. Thus, this data is stored in a memory 46 associated with the processing portion 38, configured into a form which is usable by the DMA engine 34, and then transferred and stored in the memory 42 associated with the DMA engine 34. It would be advantageous to reduce the amount of processing overhead involved in a mirroring transaction, thereby improving system performance. Accordingly, it would be advantageous to have a DMA engine which does not require a processing portion to create a DMA table. Furthermore, it would be advantageous to reduce internal memory required in a DMA engine, thereby reducing the silicon area required for such a DMA engine.